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[Program doc] 8bitmultiplicatin

Description: it is a 8 bit multiplication vhdl program.sorry ,my english is poor ,but my programmor is used.-it is a bit multiplication 8 vhdl program.s orry, my english is poor. but my programmor is used.
Platform: | Size: 8192 | Author: songzhigang | Hits:

[Other] lattice_sdram_source_code

Description: lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Platform: | Size: 31744 | Author: dido wang | Hits:

[Algorithm] data_convert

Description: 十进制小数转化二进制小数(补码形式输出),对RAM或ROM设置初值极其方便-decimal metric system conversion binary decimal (Complement forms output), the RAM or ROM set initial extremely convenient
Platform: | Size: 1024 | Author: 华少洪 | Hits:

[VHDL-FPGA-Verilog] DDS_sin

Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
Platform: | Size: 8192 | Author: sarahyu | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[VHDL-FPGA-Verilog] Sobel--Image_Filter_An_Image_filtering_VHDL

Description: Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel-- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monitor.zip
Platform: | Size: 316416 | Author: 严刚 | Hits:

[Multimedia Develop] VBuffer_1c6

Description: 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计　是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
Platform: | Size: 4133888 | Author: 刘留 | Hits:

[VHDL-FPGA-Verilog] BRAM2DRAM

Description: FPGA内嵌的BRAM资源很少，此代码为DRAM代码风格，可以极大程度上减少FPGA内嵌资源的消耗。txt文档中含源代码，直接粘成vhdl即可-FPGA embedded BRAM few resources, the code for the DRAM code style, you can significantly reduce resource consumption embedded FPGA. txt document containing the source code directly into VHDL can be sticky
Platform: | Size: 2048 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] double_RAM

Description: 在modolsim平台下仿真完成了一个双端口RAM的实现，希望有用。-Simulation platform in modolsim completed a dual-port RAM realize the hope that useful.
Platform: | Size: 89088 | Author: 陈曦 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ICL7135

Description: 双口RAM程序实例-Dual-port RAM instance
Platform: | Size: 15360 | Author: 赖永仲 | Hits:

[Other] ramchoice

Description: 多总线切换的VHDL代码。可用于多RAM的管理。-Multibus VHDL code switching. RAM can be used for multi-management.
Platform: | Size: 1024 | Author: 祝箭 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[Other Embeded program] DDram

Description: 07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码-07 National Undergraduate Electronic Design Contest winning entries C title peripheral interface FPGA dual-port RAM part of source
Platform: | Size: 1024 | Author: SRY | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[Other] MEALY

Description: MEALY状态机的输出是现态和输入的函数.在SRAM控制器状态机中,写有效WE不仅和WRITE状态有关,还和总线命令WRITE_MASK有关.这样,输出WE信号按设计要求表示为现态WRITE和现态输入WRITE_MASK的函数.本程序基于VHDL,开发环境为MAXPLUS2-Mealy state machine output is now a function of state and input. In the SRAM controller state machine, the writing is not only effective WE and WRITE state, but also and bus-related WRITE_MASK command. In this way, WE output signal according to design requirements that the current state WRITE and is a function of state input WRITE_MASK. This procedure based on VHDL, development environment for MAXPLUS2
Platform: | Size: 29696 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] acordwithram

Description: 一个牛人写的很快且不用状态机的动态RAM接口,VHDL编写-A cow were to write quickly and do not have the state machine dynamic RAM interface, VHDL prepared
Platform: | Size: 6144 | Author: john | Hits:

[VHDL-FPGA-Verilog] SDRAMconntrol

Description: SDRAM控制器的设计与VHDL实现 是pdf格式的。在工程中实现过-SDRAM Controller Design with VHDL realize is pdf format. In the projects implemented
Platform: | Size: 138240 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] VHDL_Programming_Examples

Description: vhdl例程,给出了许多VHDL例程,有参考价值,个人认为-VHDL routines, given a number of VHDL routines, there is reference value, individuals consider
Platform: | Size: 173056 | Author: 辜小兵 | Hits:

[VHDL-FPGA-Verilog] VHDL_Programming_Examples_2

Description: vhdl例程,给出了许多VHDL例程,有参考价值,个人认为，刚才上载的第2部分。-VHDL routines, given a number of VHDL routines, have reference value, personal opinion, just uploaded part 2.
Platform: | Size: 168960 | Author: 辜小兵 | Hits:

[VHDL-FPGA-Verilog] la_usb-SPISRAM

Description: 有关到SRAM的VHDL程序,也涉及到USB接口，希望对大家有所帮助-Related to the SRAM of the VHDL process involves the USB interface, and they hope to help everyone
Platform: | Size: 2048 | Author: 李锐 | Hits:
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